1. Field of the Invention
The present invention generally relates to semiconductor chips, and more particularly to semiconductor chips having a plurality of bonding pads on one surface, whose length, width and shape are modified in order to accomplish more precise interconnections with bonding wires and to achieve greater reliability for electronic components containing the chips.
2. Description of The Related Art
Semiconductor devices are progressing toward higher mounting density, higher capacity, and greater miniaturization of each semiconductor chip, in order to meet pressing demands for smaller, multifunctional electronic components. As more functionality has been built into each chip, the number of the bonding pads has increased which increases the size of the chip, resulting in an increase in the manufacturing cost of each semiconductor chip. Costs can be reduced if more bonding pads can be fit per unit length of the semiconductor chip's edge.
There is a limit to decreasing the pitch of bonding pads, i.e. the spacing between neighboring bonding pads. When the bonding pads have a pitch that is too fine, the accuracy of bonding between the bonding pads and corresponding inner leads is reduced, and electrical defects can occur. Electrical defects include shorts between adjacent bumps of bonding material that connect one inner lead wire to one bonding pad. Electrical defects also include insufficient shear strength of a bump due to insufficient contact area between the bump and the bonding pad. Insufficient shear strength leads to increased chances that the connection between a lead wire and a bonding pad will be broken.
Several terms used throughout the specification are defined herein. The term "bump" refers to the bump or small ball of bonding material that electrically connect a bonding wire to an upper surface of a corresponding bonding pad. The term "bump shear strength" refers to the shearing force on the bump necessary to separate the bump from the bonding pad. "Bump shear gram" defines the weight of the small ball having a specific "bump shear strength".
The distance between confronting sides of adjacent pads is called the "gap pitch," and the distance between corresponding parts of adjacent pads is called a "total pitch." The unit of distance marking the dimensions of the components in the specification and drawings is .mu.m, unless otherwise indicated.
Furthermore, each bonding pad has four sides. An outer side is closest to the edge of the chip, and an inner side is farthest from the edge of the chip. Each pad has one or two confronting sides facing another pad in the row of pads. End pads have only one confronting side, and interior pads have two confronting sides. The fourth side of each end pad is unnamed.
For example, a semiconductor chip may be specified as follows:
1) The position of the bonding pads: rows on all four edges of the chip PA1 2) The number of the bonding pads: 208 pads (52 per edge * 4 edges) PA1 3) The total pitch along each edge: 70 .mu.m
FIG. 1 is a plan view depicting a conventional semiconductor chip and FIG. 2 is a enlarged plan view of the part `A` in FIG. 1. FIG. 3 is a cross-sectional view taken along the line 3--3 of FIG. 2.
Referring to FIG. 1, FIG. 2, and FIG. 3, bonding pad rows, each comprising a plurality of bonding pads 12 having a square shape, are formed on the four edges of an upper surface of a semiconductor chip 10. The bonding pads 14, which are formed on both ends of the row of the bonding pads 12, are referred to as "end bonding pads". The gap pitch of the pads 12, 14 in a row is 6 .mu.m. Passivation layers 16 are formed on upper surfaces of the bonding pads 12 and the end bonding pads 14 so as to expose the central parts of the pads 12A, 14A. The distance along each side of the pads 12, 14 is 64 .mu.m, while the distance across the exposed part of the pads 12A, 14A is 54 .mu.m. An oxidation layer (SiO.sub.2) 18 is interposed on the pads 12, 14 under the passivation layer 16 to prevent stress generated by the hardening of the passivation layer.
FIG. 4 is a perspective view depicting the electrical connections between the conventional semiconductor chip 10 of FIG. 1 and a lead frame. FIG. 5 is an enlarged plan view of the part `B` in FIG. 4 showing the bump 42 electrically connecting the lead wire 40 to the bonding pad 12, 14. FIG. 6 is a schematic view depicting the dimensions of the bump 42 and the bonding pad 12, 14.
Referring to FIG. 4 and FIG. 5 a lower surface of the semiconductor chip 10 is attached to an upper surface of the die pad 20 of the lead frame, and the bonding pads 12, 14 formed on the upper surface of the semiconductor chip 10 are electrically connected to corresponding leads 30 of the lead frame by electrical connection means such as bonding wires 40. The connection between the wire 40 and the bonding pad 12, 14 is effected by a small bump 42.
In FIG. 6, the exposed bonding pads 12A and the exposed end bonding pads 14A have the same area given by 54 .mu.m * 54 .mu.m. The minimum diameter of the respective bump 42 indicated by an internal dotted line circle is 44 .mu.m, and the maximum diameter of the respective bump 42 indicated by a larger solid line circle is 54 .mu.m. In other words, the diameter and tolerance of the bump 42 is 49.+-.5 .mu.m. The minimum diameter is required to produce a bond with enough bump shear strength to reliably keep contact with the bonding pad 12, 14. The maximum diameter is required to inhibit adjacent bumps from spilling over the passivation layer, possibly contacting each other, and causing electrical shorts.
Consequently, the distance between two neighboring bumps 42, which are bonded to the upper surface of a corresponding one of two bonding pads 12, or the bonding pad 12 and the end bonding pad 14, is 6 .mu.m at the minimum, even if each bump 42 is displaced from the center by up to 5 .mu.m. This inhibits electrical shorts. When the bumps 42 are formed farther offset from the center of the bonding pads 12, 14 so that the bump is partly on the semiconductor chip 10 the bump shear strength may become insufficient. For example, when 25% or more of the area of the bump 42 deviates from the bonding pads 12 or the end bonding pads 14 the bump shear strength is insufficient.
In other words, when the bumps 42 of the semiconductor chip 10 are not exactly aligned with the corresponding upper surfaces of the interior bonding pads 12 or the end bonding pads 14, but partly deviate from the interior bonding pads 12 or the end bonding pads 14, electrical shorts or insufficient bump shear strengths occur.
Because it is difficult to exactly control the bump position due to limitations of the bonding wire equipment, the described defects do occur in the conventional semiconductor and can be expected to occur more frequently as the gap pitch and bonding pads are made smaller to accommodate an increased bonding pad density.